The basic memory cell typically used in megabit dynamic random access memories (DRAMS) is an n-channel metal oxide silicon (MOS) transistor having an output thereof connected to a capacitor with the transistor and capacitor both being formed in a common semiconductor body. This cell is typically known as a single transistor memory cell. In response to a need for larger and larger DRAMS, the single transistor memory cell has been reduced in size (i.e., scaled down) so as to facilitate a greater number of memory cells being formed in a given area of semiconductor material. One serious problem with this approach is that the amount of signal (charge) stored in this memory cell is a function of the physical size of the capacitor. As the cell is scaled down in size, the size of the capacitor is corresponding reduced and thus the capacitance thereof is reduced. One solution to this problem is the use of trench capacitors which are formed relatively deeply into the semiconductor body as so to increase the capacitance of the capacitor. As technology moves from 16 million bits of memory on a single integrated circuit chip to 64 million and then to 256 million, it becomes more and more difficult to provide the necessary minimum cell capacitance. Therefore, three dimensional structures, such as trench or stacked capacitors, are used as the storage capacitor. Furthermore, because of the tendency towards lower power supply voltages, the available output signals from the memory cells are corresponding reduced. This places higher and higher demands on sense amplifiers (signal sensing circuits) used with the memories which increases the physical size and electrical complexity thereof.
A new solution to the problem of size of the capacitor of the switched capacitor memory cell is the use of a gain memory cell of the type described in an article entitled "Fully Scalable Gain Memory Cell For Future DRAMS" by W. H. Krautschneider, L. Risch, K. Lau, and D. Schmitt-Landsiedel, published in Microelectronics Engineering Vol. 15 (1991), pages 367-370, which is incorporated herein by reference. The gain memory cell consists of first and second serially coupled MOS transistors with a diode coupled between the gate and source of the first transistor whose drain is coupled to a power supply having a voltage of +VDD. A gate of the second transistor is coupled to a control line which is denoted as a word line, and the source is coupled to a bit line. The drain of the second transistor is coupled to the source of the first transistor. It is to be appreciated that the output terminals, denoted as the drain and source, of an MOS transistor reverse as current flowing therethrough reverses. Logic information is stored in the gain memory cell as a function of charge on the gate of the first transistor. The first transistor is used as an amplifying device so that the output signal (i.e., charge from the cell) is much greater than the charge stored in the cell. This output charge (signal) is essentially being supplied from the power supply coupled to the drain of the first transistor. Accordingly, the output charge, and the corresponding generated voltage of a capacitor coupled to the bit line, increases. This generates a need for new and potentially less complex sense amplifiers (signal sensing circuits).